1. Field of the Invention
The present invention relates to a technique of holding data related to a circuit operation.
2. Description of Related Art
In a one-chip microcomputer and a system LSI mounted with a peripheral function macro, a technique of holding data indicating events such as an operation status and an unordinary status (error) of the function macro is used. Flags indicating such data are collected at one location or registers of as smaller number as possible. When such an event has occurred, these flags are set to “1”.
When a plurality of unordinary statuses (errors) have occurred at a same address, in order to recognize the details of unordinary statuses and adequately find a solution, it is desirable that an order is indicated in which the flags are set to “1”.
As a related art, an error detecting circuit described in Japanese Patent Publication (JP-A-Showa 63-73435) is known. FIG. 1 shows a configuration of this error detecting circuit. The error detecting circuit includes SR latches holding an error occurrence state, a counter (timer) generating an error occurrence order; and registers (latches) receiving a count value when an error has occurred First, in response to a reset signal, error flip-flops 101-i (i=1 to n), a counter 102, and register 103-i are initially set to “0”. If an error signal 111-1 is generated, the register 103-1 holds “0” while the registers 103-2 to 103-n are incremented to the value of “1”. Next, if an error signal 111-2 is generated, the register 103-1 holds “0”, the register 103-2 holds “1”, and registers 3-3 to 3-n are set to “2”. By repeating such an operation, the error occurrence order can be found even when a plurality of errors have occurred.
However, the above Japanese Patent Publication does not describe a method of reading the error occurrence order in detail. In the circuit described in the above Japanese Patent Publication, a CPU needs to read all the registers in order to completely recognize the error occurrence order. When a plurality of errors have occurred at a same time, a plurality of registers must hold a same value. Thus, an increase in the number of errors requires a long time for judgment on whether or not a system unordinary status is present and a recovery operation. For example, where a total number of errors is n, in order for the CPU to find a first error and a second error, a read command needs to be issued n times. Therefore, when a CPU clock frequency is relatively lower than a clock frequency of a peripheral macro, the above problem may become more remarkable.